The present invention relates to printed circuit board interconnects and in particular the present invention relates to printed circuit board interconnects with limited overshoot variations and reflections.
One of the design challenges facing the electronics industry is the reflection on transmission lines (e.g., traces on a PCB (printed circuit board)). Not limiting these reflections can cause problems that can have an impact at the digital level, including increased delays, increased overshoot and increased ringing (i.e., oscillations) in the signal response. FIG. 1 illustrates a typical system involving these reflection issues, wherein two integrated circuits are operatively coupled by a transmission line. FIG. 1 includes integrated circuit 102, integrated circuit 108, transmission line 110, output node 104 and input node 106. In general, a signal travels from output node 104 to input node 106, and each time there is a reflection from input node 106 back to output node 104 or vice versa, causing a doubling of the total voltage. Integrated circuit 102 has an impedance of Zbuf at output node 104. Integrated circuit 108 is operatively coupled to integrated circuit 102 through transmission line 110 having a characteristic impedance, Zo.
FIG. 2 is a graph of the voltage over time of the voltages at output node 104 and input node 106 with Zbuf greater than Zo causing the initial step voltage at output node 104 to be less than Vcc/2. This in effect causes a sequence of stair steps between the voltage at output node 104 and the voltage at input node 106 wherein the voltage at output node 104 has an initial step and the voltage at input node 106 jumps to twice that voltage with the refections between output node 104 and 106 building up until voltages reach Vcc (i.e., stair-stepping behavior). Once Vcc is reached, the system stabilizes. The problem with this system is the very long delay between the initial step and the stabilizing point at Vcc.
FIG. 3 is a graph of the voltage over time of the voltages at output node 104 and input node 106 with Zbuf less than Zo causing the initial step voltage at output ode 104 to be greater than Vcc/2. This forces the voltage at input node 106 to overshoot the desired voltage, Vcc (i.e., overshoot behavior). As shown, the voltages at output node 104 and input node 106 continue to bounce above and below Vcc until reaching Vcc and thus stabilizing at some later point in time.
These reflection problems have been addressed by controlling impedance, Zbuf, at output buffer 104 using driver impedance matching wherein the output impedance, Zbuf, matches the characteristic impedance, Zo. This impedance matching forces the initial voltage at node 114 to be Vcc2. With this voltage, Vcc/2, being transmitted down transmission line 110, this voltage arrives at input node 106, where a reflection is produced. Adding this reflected voltage to the initial voltage at input node 106, both of which are also approximately xc2xd of Vcc, the total voltage at input node 106 is approximately equal to Vcc. Moreover, the reflected voltage at input node 106 (Vcc/2) is transmitted back toward output node 104 causing the voltage at output node 104 to add this voltage to the voltage already residing at output node 104 (Vcc/2) to provide a total voltage of Vcc at output node 104. Thus the voltage at input node 106 is twice the initial step voltage at output node 104. In summary, making the voltage at output node 104 Vcc/2 causes the voltage at input node 106 to be Vcc. Once Vcc is reached the system is stabilized. Therefore, at input node 106, no further reflections are produced.
FIG. 4 is a voltage-current (V-I) curve wherein the output impedance, Zbuf and the characteristic impedance, Zo, match through the use of digital logic compensation circuitry to compensate based on Zo. This circuitry senses the level of the characteristic impedance and changes the V-I curve by controlling how much current comes out of the buffer to maintain the voltage at Vcc/2. In particular, FIG. 4 illustrates three different V-I curves (curves 406, 408 and 410) which are varied by the digital control circuitry in the range between load lines 402 and 404 to match the output impedance to the characteristic impedance. In addition to the costs involved with this compensation circuity, this solution also requires several clock cycles to program the buffer to the correct configuration to match the impedances between the buffer and the transmission line.
Elimination of reflections also addresses another design challenge facing the electronics industry: an interconnect-related effect called Inter-Symbol Interference (ISI). ISI occurs at times when there is ringing (oscillation) on one data cycle (bit) which causes a change in the timing of any subsequent bits. ISI affects signals when the driver does not reach steady state prior to the next switching cycle. Additionally, ISI introduces greater skew into the timing of a system. Skew is a difference in arrival times (i.e., the difference in flight times) between two signals in a system when the two signals are employed to remain synchronized within close tolerances.
Even though using current compensated buffers has been shown to be effective in impedance matching, this approach is expensive and limited in its performance in that it typically can only achieve interconnect skews of 500 pico-seconds (psec). For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a low-cost circuit which better controls the above-described overshoot and ringing, while also providing a reduction of the interconnect skews.
In one embodiment, an integrated circuit includes a signal source. Additionally, the integrated circuit includes an output buffer operatively coupled to the signal source. The output buffer generates an output signal in response to a voltage transition at the signal source. Moreover, the output buffer can be coupled to a transmission line terminated with a circuit, wherein the transmission line has a characteristic impedance which can vary over a range of A to B. The output buffer has a voltage-current (V-I) curve having a voltage that is approximately constant over the range of A to B, wherein the output signal can be transmitted to the circuit such that the output signal reaches a stable voltage after one round trip.